The present invention relates to VDMOS transistors, and particularly to VDMOS transistors integrated in so-called mixed-technology (smart-power) devices, where VDMOS transistors are fabricated together with CMOS and/or DMOS and/or bipolar transistors, etc.
In making discrete or integrated VDMOS transistors one of the main problems consists in simultaneously optimizing the breakdown voltage (which should be as high as possible) and the ON-resistance of the device (which should be as low as possible). Particularly in the case of integrated VDMOS transistors fabricated with a mixed-technology process (for integrating on the same chip also CMOS, DMOS and bipolar transistors, etc.), the output impedance of the VDMOS device assumes a more critical character than in the case of discrete VDMOS transistors, because of the additional contributions to the internal resistance that inevitably are introduced by the necessity for front-side contact. (Typically deep-drain connection diffusions are used for gathering the current at the surface of the integrated device.) FIGS. 1 and 2 show this substantial difference between a conventional discrete VDMOS structure (FIG. 1) and a conventional integrated VDMOS structure (FIG. 2).
As is well known in the art, an integrated VDMOS transistor commonly has an inter-digitated structure, as obtained by alternating finger-like matrices of source cells with finger-like drain-connection diffusions (also referred to as "sinker" diffusions) that reach down in depth as far as to intersect a buried layer, which acts as a collector of drain current. Peripheral cells of each matrix of cells, adjacent to the relative drain-connection diffusion and separated from the latter by a strip of field oxide, represent so-called edge portions. It is at the edge portions, under reverse bias conditions, that the maximum intensity of electric field is experienced. Therefore, these peripheral zones are critical as far as the breakdown voltage of the drain/source junction (body/drain) is concerned.
The optimization of the two basic parameters of a VDMOS transistor depends on the adoption of an edge configuration apt to achieve a breakdown voltage as close as possible to the theoretical breakdown voltage of a planar junction of infinite size, and from appropriately dimensioning and determining the electrical characteristics of the epitaxial layer (i.e. thickness and bulk resistivity).
A known and widely employed edge configuration for attaining an acceptably high breakdown voltage of the body/drain junction of a VDMOS structure is characterized by the presence of a biplanar field-plate structure, commonly of polycrystalline silicon, patterned to lie on the thin gate oxide layer (having a typical thickness between 50-100 nm) of the edge cells and to extend over the relatively thick, field-isolation, dielectric layer (having a typical thickness of about 1 .mu.m), as schematically shown in FIG. 3.
This solution does not impede the operation of the peripheral cells of each source finger of the interdigitated structure of the VDMOS transistor. However, at relatively high reverse bias voltages across the body/drain junction, an intense electric field still occurs at the surface of the semiconducting monocrystalline substrate under the transition zone between the thin dielectric gate layer and the relatively thick dielectric field-isolation layer. Electric field contours are shown in FIG. 4, as obtained by computer simulation, in proximity to such a critical edge zone of an integrated VDMOS structure provided with a biplanar field-plate.
The high electric field intensity that occurs at the interface between the semiconductor and the dielectric layers may still be a cause of instability in the breakdown characteristics and makes the structure particularly sensitive to defects and accidental contamination of the dielectric layers.
Other techniques besides the use of field-plates are known for reducing the electric field magnitude in the edge zone. One of these other solutions is schematically depicted in FIG. 5. This technique contemplates the formation of a deep edge diffusion (a p+ diffusion in the example shown) that intersects and extends beyond the body diffusion (P-body). In practice, as may be easily observed in FIG. 5, the p+ diffusion profile used for making a p+, body-contact, region is also used for making this p+ edge diffusion in the peripheral cells. The increase of the radius of curvature of the diffusion profile that is so obtained along the edge region, produces a decrease (for a given voltage) of the electric field intensity in the curved region of the body/drain junction and therefore an increment of the breakdown voltage. However, this solution inhibits the formation of a secondary channel (i.e. lateral conduction through the peripheral cells facing the drain-connection diffusion), and this implies a depression of the electrical performance of the device, i.e. an increase of the internal resistance, especially in the case of an integrated VDMOS structure.
Finally it may be recalled that in the case of mixed-technology integrated circuits (e.g. in smart-power devices), for increasing the density of the cells of the integrated VDMOS structures, as well as of other components integrated in the same chip, the fabrication technology normally employs process steps derived from the so-called high-density CMOS processes. In particular:
The dielectric field-isolation layer is commonly realized by a LOCOS.TM. technique, rather than by etch-patterning a thick oxide layer previously grown over the whole surface. PA1 CMOS structures commonly use field-isolation diffusions (P-field or N-field) under the edge portions of a thermally grown field oxide, for increasing the parasitic threshold voltage under the dielectric field-isolation layer, and thus more effectively isolating the CMOS transistors from each other. PA1 Reduced junction depths are normally used, due to the need for compactness of the high-density CMOS integrated structures.
Generally, in fabricating high-density, mixed-technology devices, certain geometrical and/or technological restraints are encountered that in practice limit or exclude the possibility of implementing certain optimization techniques of the integrated structures, in particular of VDMOS structures. Notably, this is the price to pay for making the formation of technologically different structures in a single chip mutually compatible. Particularly in the case of VDMOS transistors, relatively deep, body-contact diffusions are no longer usable. Instead, a relatively shallow diffusion, which is also used for making the source and drain regions of CMOS transistors, is normally used as a body-contact region. As a consequence, the technique discussed above that contemplated the formation of a relatively deep diffusion along the edge portions of the VDMOS structure, for increasing the radius of curvature of the body/drain junction profile (e.g. P-body/n--EPI) and reducing the electric field intensity at the surface of the semiconductor in the transition zone between the gate oxide and the field oxide, is no longer applicable, unless additional masks and process steps are introduced.
The present invention provides a VDMOS transistor having a modified edge configuration capable of increasing the breakdown voltage without penalizing the internal resistance of the device. The invention is particularly useful for smart power devices.
A new method for significantly increasing the effectiveness of a biplanar field-plate without lowering the electrical performance characteristics of a VDMOS transistor is advantageously provided by the disclosed innovations. Notably, the new method of the present invention does not require the formation of a relatively deep edge diffusion, and may be implemented also for integrated VDMOS structures in high-density, mixed-technology, devices. In these applications, the method of the invention will not require the use of additional masks and process steps.
Basically, the invention may be practiced through a simple modification of a mask or of masks that are normally used in a standard fabrication process and the structural modification that is produced does not imply any substantial alteration of the electrical performance of the device, though attaining the effect of a marked increase of the breakdown voltage and of the reliability of the VDMOS structure.
These effects are obtained by establishing an electrical connection between the source region of a VDMOS transistor and a field-isolation diffusion, e.g. a P-field region, purposely formed under the edge of the thick, dielectric, field-isolation layer that border a matrix of source cells and that, in the case of an integrated VDMOS, may separate a matrix of source cells from a drain-connection (sinker) diffusion. The field-isolation diffusion may extend under the transition zone between a relatively thick field oxide layer and a relatively thin gate oxide layer present on the active area of a peripheral source cell, i.e. in the zone that is actually topped by the biplanar field-plate structure.
It has been found that by providing the VDMOS structure with such a field-isolation diffusion and by tying the potential of the field-isolation diffusion to the source potential of the device, a marked reduction of the maximum electric field intensity in the curved zone of the body/drain junction of the device (i.e. the edge zone) is achieved as well as a sensible increase of the breakdown voltage. For example, in the case of a VDMOS formed in an epitaxial layer having a thickness between 9 and 11 .mu.m and a bulk resistivity between 1.1 and 1.6 .OMEGA.-cm, the breakdown voltage may be increased from about 75 V to about 100 V.
According to a preferred embodiment of the invention, a body diffusion of a peripheral source cell every given number of peripheral cells of a matrix constituting a finger of an inter-digitated structure of an integrated VDMOS transistor is extended until it intersects a field-isolation diffusion formed under a strip of a field oxide separating the peripheral source cells from a drain diffusion. The field-isolation diffusion may extend slightly beyond the geometrical projection of the edge of the thick field-isolation dielectric layer.